The present invention generally relates to metal-semiconductor field effect transistors (MESFET) and more particularly to a compound semiconductor MESFET device constructed on a substrate of a group III-V compound semiconductor material such as gallium arsenide (GaAs), aluminium gallium arsenide (AlGaAs), indium phosphide (InP) and the like.
Integrated circuits of compound MESFET devices have characteristically high operational speeds and are used in various information processing systems such as computers, telecommunication systems, telemetry systems and the like where a particularly high operational speed is strongly demanded. Even in the systems and apparatuses using such integrated circuits, there is a persisting demand for miniaturization of the individual devices of the integrated circuit and for increased integration density so that still higher operation speeds are achieved.
Compound semiconductor MESFET devices are constructed on a group III-V compound semiconductor substrate defined with a channel region together with a source region and a drain region disposed on opposite sides of the channel region. In such devices, a gate electrode is provided directly on the substrate in correspondence to the channel region and a passivation film covers the gate electrode as well as the source and drain regions. In these structures, a complex stress field is created in the substrate in correspondence to edges of the gate electrode and the passivation film. Such stress field induces a piezoelectric charge in the substrate and the electrical charge thus induced in the channel region changes the operational speed of the device. In the description which follows, the problem of the piezoelectric effect which arises in association with the miniaturization of compound semiconductor MESFET devices will be explained with reference to FIGS. 1, 2(A) and 2(B) which illustrate a typical prior art MESFET device having a self-aligned structure.
Referring to FIG. 1, the transistor is constructed on a semi-insulating GaAs substrate 1 and comprises an n-type channel region 2 defined in the substrate 1, a gate electrode 3 provided on the substrate 1 in correspondence to the channel region 2, a source region 5 doped to the n.sup.+ -type and defined in the substrate 1 at one side of the channel region 2, a drain region 6 also doped to the n.sup.+ -type and defined in the substrate 1 at the other side of the channel region 2, a source electrode 8 provided on the substrate in correspondence to the source region 5 and in ohmic contact therewith, a drain electrode 9 provided on the substrate 1 in correspondence to the drain region 6 and in ohmic contact therewith, and a passivation film 7 provided so as to cover the gate electrode 3 as well as those parts of the substrate 1 extending between the gate electrode 3 and the source electrode 8 and between the gate electrode 3 and the drain electrode 9. The remainder of the substrate 1 on which the transistor is not formed is covered by a protective film 4 of silicon nitride. In the illustrated example, the gate electrode 3 is provided on the (100) surface of the GaAs substrate 1 so as to extend in the &lt;011 &gt; direction of the substrate.
When the passivation film 7 is formed of silicon nitride, the same is under compressional stress mainly due to the difference between the temperature at which the transistor is fabricated and the temperature at which the transistor is used. Responsive thereto, the substrate 1 experiences tensile stresses T at the inner edges 7a of the passivation film 7 as well as tensile stresses T' at the outer edges 7b of the passivation film 7 as illustrated in FIG. 2(A). For clarity, the source electrode and the drain electrode are omitted in FIG. 2(A). Further, the gate electrode 3 itself induces tensile stresses t at the inner edges 7a which tend to stretch the substrate. Since the tensile stresses T act from both sides of the gate electrode 3 in a direction to compress a region beneath the gate electrode 3, and since the magnitude of the tensile stresses T is generally much larger than that of the stresses t, compressive stress components .DELTA.T are created in a region C of the substrate which is slightly below the gate electrode 3 as a result of the superimposition of stress components T and stress components t. Further, a tensile stress component is created in the region C as a result of the effect of the stresses T' at the outer edges 7b of the passivation film 7 acting to stretch the substrate in the region C. Such tensile stress component is usually negligible as long as the transistor has a relatively large size and there is a relatively large distance between the region C and the edges 7b. Thus, the predominant stress in the region C in this prior art MESFET device is compressive.
When a group III-V compound substrate having a zinc blend structure is subjected to such a compressive stress field acting in the &lt;011&gt; direction which is perpendicular to the elongating direction of the gate electrode 3 extending in the &lt;011 direction, a displacement of the negatively charged arsenic atoms relative to the positively charged gallium atoms is caused in the substrate, and responsive to such displacement, a negative piezoelectrical charge appears in the region C. Such a negative charge in the region C, which extends into channel region 2, induces a stationary depletion region, particularly in the lower part of the channel region 2, as a result of the expulsion of carrier electrons. Thus, the effective channel thickness is decreased and the operational speed of the transistor is increased. Accordingly, the prior art MESFET device of FIG. 1 can use such piezoelectrical charge to increase the operational speed of the transistor.
On the other hand, when the size of the transistor is reduced for further improvement of the operational speed, the distance between the outer edges 7b of the passivation film 7 and the gate electrode 3 is decreased and the contribution of the tensile stresses T' to the stress field in the region C is correspondingly increased. As a result, a state is created in which tensile stresses become predominant in the region C when the size of the MESFET is made excessively small. In such a state, a positive piezoelectrical charge appears in region C and the depletion region no longer exists. Thus, such miniaturization tends to decrease rather than increase the operational speed of the transistor. A more detailed description of the piezoelectric effect in group III-V compound semiconductor crystals can be found in a paper by Booyens et al. (Booyens, H., Vermaak, J. S., Proto, G. R., "DISLOCATIONS AND THE PIEZOELECTRIC EFFECT IN III-V CRYSTALS", J. Appl. Phys. Vol. 48, No. 7, July 1977).
FIG. 2(B) illustrates a case in which silicon oxide is used as the passivation film 7. In FIG. 2(B), parts which correspond with parts in FIG. 2(A) are given identical reference numerals and description thereof will be omitted. It is assumed in this case also that the gate electrode 3 extends in the &lt;011 &gt; direction on the (100) surface of the gallium arsenide substrate 1 similarly to the case of the transistor of FIG. 2(A).
In the transistor of FIG. 2(B), the silicon oxide passivation film 7 experiences tensile stresses. In other words, the substrate 1 experiences compressive stresses in source region 5 and in drain region 6 and stress components T.sub.0 are created at the inner edges 7a of the passivation film 7 to act as tensile stresses in channel region 2 and stress components T.sub.0 ' are created at the outer edges 7b of the passivation film 7 to act as compressional stresses at the channel region 2. Further, tensile stress components t are induced similarly to the case of FIG. 2(A) between the gate electrode 3 and the substrate 1. Thus, large tensile stress components .DELTA.T' appear in the region C as the sum of the stress components T.sub.0 and t, and the stress components .DELTA.T' act in an opposite sense relative to the stress components .DELTA.T of FIG. 2(A). In other words, the stress components .DELTA.T' act to deteriorate the operational speed of the transistor.
In this case, the compressional stress components T.sub.0 ' at the outer edges 7b of the passivation film compensate the tensile stress components .DELTA.T' to some extent, particularly when the size of the transistor has been decreased. However, the effect of the tensile stress components .DELTA.T' in the region C is generally much larger than the effect of the compressional stress components T.sub.0 ' and therefore an undesirable decrease in the operational speed of the transistor cannot be avoided.